1. Technical Field of the Invention
The invention concerns an error testing and diagnostic device for an electronic data processing system comprising at least one processor, one main storage and one maintenance and service processor interconnected by a fast system bus.
2. Description of Related Art
The testing of very large scale integrated logic and storage circuits on chips, of which electronic controls, processors and other data processing systems consist, is based to a considerable degree on the accessibility (observability, controllability) of the totality of the storage elements (bistable circuits, flip-flops) on the chip. It is here where problems are encountered, because digital systems require an extremely high error coverage, and the testing of very large scale integrated circuit structures is time-consuming and expensive owing to the circuit density of such VLSI chips (VLSI=Very Large Scale Integration). The processing units, such as the microprocessors, consist of or comprise highly complicated chips which have to be tested such that the large number of states bistable storage elements are capable of assuming and the even larger number of state sequences these processor storage elements are capable of assuming during the execution of program routines are duly taken into account.
Looking upon a micro instruction as a finite functional entity, then the testing of the generally well specified and well defined micro instruction functions, such as the setting of the state storage locations of an arithmetic and logical unit (ALU), becomes an easily assessable problem after the execution of an add micro instruction. Difficulties are encountered, however, if all possible secondary functions of that add micro instruction have to be tested as well, such as whether the state of a bistable storage element, indicating bus requests during the execution of such an add micro instruction, has changed or not.
The secondary functions generally require a large number of storage elements which are associated with the data flow and the control logic of the processor. Generally, even when special micro instructions are used, these storage elements are not directly accessible for test purposes, without changing the current states of all storage elements serving as state indicators.
Testable, very large scale integrated logic structures and system architecture frequently use what is known as LSSD (Level Sensitive Scan Design) rules, according to which, for example, a logic subsystem is signal level sensitive if, and only if, the response to an input signal change in the steady state is independent of circuit and line delays in that logic subsystem (cf. "A Logic Design Structure for LSI Testability" by E. B. Eichelberger--Proceedings of the Design Automation Conference, No. 14, 20 to 22 June 1977, New Orleans, Louisiana, pp. 462 to 468).
Based on those LSSD rules, the totality of the storage elements are made observable and controllable in that the master/slave flip-flops, which are logic components and which are also positioned between the logic stages, are interconnected in the test mode to form one shift register chain or several such chains. These chains are used to shift test and result patterns into and out of the very logic, respectively.
The shift register chains may also be used to shift complete flip-flop or register status data into or out of complex logic groups, such as chips or modules, which are separated from each other with regard to their packaging. This shift register approach has the advantage that only relatively few input/output terminals are required and that there is a high degree of flexibility between the various packaging levels if all first packaging level shift register chains are connected to a common second packaging level shift register chain, etc., without affecting the chip logic.
As the storage elements of a processor consist almost exclusively of shift register stages, the secondary functions can be tested either by an integrated maintenance and service processor or by a connectable separate tester, in that, before or after execution of the micro instruction to be tested, the centers of the bistable storage elements, interconnected for shift register testing, are shifted into the maintenance or service processor or the tester where the state differences are compared with given desired values.
A further significant improvement of the diagnostic capabilities of micro instruction tests for the exchange of data and instructions in processing units and between processors is conceivable by applying the test routines to even smaller functional entities, such as the clocking steps of the micro instruction to be tested. Such an approach would lead to a considerably improved error coverage of automatic tests.
The aforementioned test methods necessitate, however, a high-speed transfer of states stored in a multitude of bistable circuit elements. This transfer would have to be effected by a maintenance and service processor or a factory tester which owing to the known slow test network and the serial shift mechanism are unsuitable for that purpose. Apart from this, the clocking speed of the shift mechanism cannot be increased further despite the very fast technology of processor chips, as the shift ring comprises two slower networks, one extending from the processor or the processing unit to the maintenance and service processor and the other from the maintenance and service processor to the processor (cf. FIG. 1, lines 14 and 13).
Generally, however, data processing systems are provided with parallel high-speed system buses interconnecting the different units, such as the processors 9, 10, . . . n, the main storage 3, the main storage control 4, the input/output device control 5, and the maintenance and service processor 6, as shown in FIG. 1. In known data processing systems, however, these system buses are not provided for the maintenance and service processor to have direct access to the bistable elements of the processor containing, among other data, the status information.
One exception is the testing and diagnostic device for digital computers described in the European patent application No. 83 105 172.7. In the case of the data processing system covered by that application, the storage elements (flip-flops) interconnecting the logic subsystems during normal operation are linked for error testing and diagnosis in the form of an addressable matrix, so that the maintenance and service processor provided for is capable of transferring on the fast system bus address information for controlling the individual storage elements of the matrix and test data for entry into the storage elements of the matrix, as well as test control and clock information which is fed to the unit to be tested. Furthermore, after the logic subsystems have been tested, their result data are entered into the connected storage elements and, using the system bus and the address and control information transferred thereon, are subsequently fed from the storage elements, interconnected in the form of a matrix, to the maintenance and service processor.
As the storage elements of the matrix are exclusively made up of so-called master flip-flops, they cannot be realized as usual by means of shift registers consisting of master/slave flip-flops, which is very disadvantageous with many design concepts of data processing systems.
A further disadvantage of known systems is that the test bus 13, 14 has only one core which may lead to line interruptions or total failure of the test bus and thus also of the data processing system, because the maintenance and service processor, by controlling, for example, the system console along with the screen and the keyboard, generally performs, in addition to the test function, the operating function of the system.
Thus, it is a principal object of the present invention to provide a testable logic structure which is extremely fast, reliable and inexpensive, even in the test mode performed on the LSSD principle. It is another object of the present invention to provide testing apparatus wherein the test patterns and result data, which in the test mode are transferred on the very fast system bus between a maintenance processor or tester and the logic structures to be tested, are very rapidly shifted into and out of the shift chains, with the test mode being implemented via the respective bus that is still intact, irrespective of a system bus or test bus failure.
These and other objects of the present invention are achieved through the use of an error testing and diagnostic device for an electronic data processing system having at least one processor, one main storage and one maintenance and service processor interconnected by a fast system bus. For testing such structures, the known LSSD method is frequently used, wherein the storage elements of the logic subsystems are combined in the form of shift register chains for testing. To permit a fast exchange of test data on the system bus, connecting the processor to a tester, the interface register stages are also included in the shift register chain which has a garland-shaped structure and whose beginning and end are connected by a controllable switch during testing. During testing, the entry of test data and the emission of result data, which are in each case effected through the system bus, and the shift steps of the garland-shaped shift register chain overlap one another.